As a result, an asymmetric
delay may cause an o?®set to the clock that can
not be detected by a variance type method [10].
If the asymmetric delay is static, the time o?®set
between any two nodes is also static. The
asymmetric delay is bounded by one-half the
round trip time between the two nodes [10].
(5) Clock glitches -Clock glitches are sudden jumps in time. This
may be caused by hardware or software
anomalies such as frequency and time steps.
systems also apply to sensor networks [10]; these factors are temperature,
phase noise, frequency noise, asymmetric delays, and clock glitches, and they
are described in Table 1.
Since sensor nodes are randomly deployed and their broadcast ranges are
small, communications between the sensor nodes may rely on multi-level hierarchical
architecture. Also, other influencing factors may shape the design
of the time synchronization protocol. For example, larger asymmetric delays
may cause more constant o?®set. In addition, the links between the sensor
nodes may not be reliable. As a result, the influencing factors may have to
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be addressed di?®erently. In the following section, the challenges in designing
a time synchronization protocol are discussed.
4 Design Challenges
In the future, many low-end sensor nodes will be deployed to minimize the
cost of the sensor networks. These nodes may work collaboratively together
to provide time synchronization for the whole sensor network.
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